1. Field of the Invention
This invention relates to a latch circuit used for a semiconductor integrated circuit device or the like.
2. Background Art
FIG. 12 shows a general master/slave latch circuit. In FIG. 12 is shown an input A to a master latch circuit M. An input B to a slave latch circuit S is the output of the master latch circuit M. Also shown are an output C of the slave latch circuit S and a control signal .phi.. A master input gate G.sub.5 and a slave latching gate G.sub.8 have enable state and disable states controlled by a control signal .phi. and have respective outputs 0.sub.5 and 0.sub.8. A master latching gate G.sub.6 and a slave input gate G.sub.7 have their enable states and disable states controlled by a control signal -.phi. and have respective outputs O.sub.6 and O.sub.7. The control signal -.phi. is the complement of the control signal .phi.. The master latch circuit M contains a buffer B.sub.3 and the slave latch circuit S contains a buffer B.sub.4.
FIG. 13 is a table indicating the states of the gates G.sub.5 through G.sub.8 and of the latch circuit outputs B and C with the states of the control signal .phi..
The operation of the conventional master/slave latch circuit will be described.
When the master input gate G.sub.5 and the slave latching gate G.sub.8 are enabled by the control signal .phi., the gates G.sub.6 and G.sub.7 are disabled. As a result, the signal of the input A is applied to the output 0.sub.5 of the gate G.sub.5. Simultaneously, in the slave latch circuit S the signal of the output C existing before the change of the control signal .phi. is latched by the gate G.sub.8 and the buffer B.sub.4. When the control signal .phi. is inverted, the gates G.sub.5 and G.sub.8 are disabled while the gates G.sub.6 and G.sub.7 are placed in an enabled state. Under this condition, in the master latch circuit M, the signal of the output B existing before the control signal .phi. is inverted is latched by the gate G.sub.6 and the buffer B.sub.3. At the same time, the signal of the output B latched by the master latch circuit M is transmitted through the gate G.sub.7 in the slave latch circuit S and thus transmitted to the output C.
The conventional master/slave latch circuit suffers from a difficulty that, when the potential of the control signal .phi. becomes unstable between the "H (high)" potential and the "L (low)" potential (for instance the potential of the control signal .phi. changes slowly from "L" to "H"), the signal of the input A read into the master latch circuit M is directly transmitted to the output C of the slave latch circuit S. The signal provided at the output B (described later) is determined by which one of the outputs of the master input gate G.sub.5 and the slave latching gate G.sub.8 has the smaller output impedance. Similarly, the signal provided at the output C is determined by which one of the outputs of the master latching gate G.sub.6 and the slave input gate G.sub.7 has the smaller output impedance. These output impedances are determined depending upon performances of transistors used therein.
On the other hand, in the conventional master/slave latch circuit, in order to decrease the delay time of signal transmission from the input A to the output B and from the input B to the output C, the input gate G.sub.5 in the master latch circuit and the input gate G.sub.7 in the slave latch circuit are made large in transistor size. Also, in order to reduce the chip size of the semiconductor integrated circuit device or the like the master latching gate G.sub.6 and the slave latching gate G.sub.8 are made small in transistor size. Accordingly, in the above-described case, when the potential of the control signal .phi. is .phi..sub.3 (O&lt;.phi..sub.3 &lt;.phi..sub.O), the output impedance Z.sub.5 equal to the output impedance Z.sub.6 of the master latching gate G.sub.6. Furthermore, when the potential of the control signal .phi. is .phi..sub.4 (.phi..sub.0 &lt;.phi..sub.4 &lt;V.sub.cc), the output impedence Z.sub.7 F of the slave input gate G.sub.7 becomes equal to the output impedance Z.sub.8 of the slave latching gate G.sub.8. Therefore, when .phi..sub.3 &lt;.phi.&lt;.phi..sub.4, the output impedance Z.sub.5 of the master input gate G.sub.5 is lower than the output impedance Z.sub.6 of the master latching gate G.sub.6, and the output impedance Z.sub.7 of the slave input gate G.sub.7 is lower than the output impedance Z.sub.8 of the slave latching gate G.sub.8. As a result of this, at the output B the output O.sub.5 of the master input gate G.sub.5 is provided as a "master" output while the output O.sub.6 of the master latching gate G.sub.6 is provided as a "slave" output. Also, at the output C the output O.sub.7 of the gate slave input G.sub.7 is provided as a "master" output while the output O.sub.8 of the slave latching gate G.sub.8 is provided as a "slave" output. That is, both of the outputs O.sub.5 and O.sub.7 from the input gates G.sub.5 and G.sub.7 are provided as "master" outputs, and the signal of the input A read into the master latch circuit M is transmitted directly to the slave latch circuit output C with the result that the function of the master/slave latch circuit is not correctly performed. That is, the master/slave latch circuit operates erroneously.